Code converters



May 16, 1967 K coma CONVERTERS Original Filed March 4/1964 2Sheets-Sheet l INVENTOR LEZGRY 0% 44. ATTO NEYS United States Patent3,320,606 CODE CONVERTERS Leon Gryk, New Britain, Conn., assignor, bymesne assignments, to Royal Typewriter Company, Inc., New York, N.Y., acorporation of Delaware Continuation of application Ser. No. 349,422,Mar. 4, 1964. This application Nov. 16, 1966, Ser. No. 596,716 8 Claims.(Cl. 340347) This invention relates to code converters; moreparticularly it relates to apparatus for converting first system codesinto corresponding second systems codes characterized by its ability toautomatically generate second system precedence codes in a facilemanner.

Data processing systems generally employ binary codes to representinformation. Since the number of combinations possible in an n bit codeis 2 it has been the practice to employ two of the possible 2combinations as precedence codes thereby to permit the use of each ofthe remaining 22 combinations to designate two different characters. Forexample, codes following one of the precedence codes might representlower case information on a typewriter keyboard and the same codesfollowing the other precedence code might represent upper caseinformation on the typewriter keyboard. The difiiculty in providingapparatus for converting first system codes to second system codes,aside from the fact that many systems do not employ the same codeassignment for a particular character, resides in the fact that lowercase information in one system is likely to be upper case information inanother system. Accordingly systems for converting first system codes tosecond system codes heretofore advanced accommodated to above difiicultyonly with complex and expensive circuitry.

In accordance with the present invention the above difliculty isaccommodated by simple and inexpensive apparatus which permits of theconversion of codes of any one system to codes of any of several othersystems by the simple expedient of changing record in which first systemcodes to be converted and corresponding codes of a second system towhich the first system codes are to be converted are prerecorded.

Broadly, in accordance with the invention circuitry is provided tocompare for coincidence input and sensed prerecorded first system codes,to sense and store during the coincidence interval the prerecordedsecond system code corresponding to the coincident first system code, tothereafter determine from the prerecorded medium the precedence or caseassignment of the character represented by the stored second system codewhereby if no precedence change is dictated the stored second systemcode may be read out for reproduction or when a precedence change isdictated to generate a precedence code for reproduction and then readout the stored second system code.

An object of the invention is to provide a code to code converter withprovision for generating precedence codes in a facile manner.

Another object of the invention is in the provision of a code to codeconverter employing prerecorded records containing codes to be convertedand codes to which said first codes are to be converted whereby any codesystem may be converted to any other code system simply by changingrecords.

A further object of the invention is in the provision of a code to codeconverter whereby any code system may be converted to any other codesystem at high speeds.

A further object of the invention is to provide a code to code converterwhich is capable of converting first system codes to second system codeswherein character code assignments as well as upper and lower casecharacter assignments differ.

3,320,606 Patented May 16, 1967 A still further object of the inventionis in the provision of a code to code converter employing records havingprerecorded thereon codes to be converted and other codes to which saidfirst codes are to be converted, said prerecorded other codes beingaccompanied by prerecorded precedence information.

Still another object of the invention is in the provision of a code tocode converter wherein coincidence of input and prerecorded first systemcodes enable the readout of corresponding prerecorded second systemcodes and the generation of second system precedence codes wherenecessary.

Other objects and many of the attendant advantages of this inventionwill be readily appreciated as the same becomes better understood byreference to the following detailed description when considered inconnection with the accompanying drawings in which like referencenumerals designate like parts throughout the figures thereof andwherein:

FIGURE 1 is a schematic block diagram of a preferred embodiment of acode converter in accordance with the invention employing twoprerecorded discs; and

FIGURE 2 is a timing diagram explanatory of the operation of the FIGURE1 logic circuitry.

Referring now to the drawings wherein like reference charactersdesignate like or corresponding elements throughout the several viewsthere is shown in FIGURE 1 disc records A and B. The discs are adaptedto be synchronously driven, and to this end they may be mounted inaxially spaced relation on a motor driven shaft 2; the shaft beingprovided with a spline 3 and the discs with complementary keywayswhereby the discs are driven in fixed orientation relative to oneanother.

Disc A has prerecorded therein, as by perforating along radial lines,parallel bit code patterns 4 representing all of the characters of andin accordance with a first system code assignment. The bits of the codesare recorded in parallel circular bit tracks designated 2, 2 2 2 Due tothe fact that identical code paterns are, in most systems, employed torepresent two different characters, i.e. an upper and a lower casecharacter, and are distinguishable by type basket operating caseprecedence or letters and figures precedence codes, in order torepresent all of the first system characters requires that each dualmeaning first system code be recorded twice in the disc A. In accordancewith the invention identical code patterns recorded on the disc A aredistinguishable by the presence or absence of a hole accompanying thecode patterns in a precedence or case designator track 5. As viewed inFIGURE 1 upper case character representative or Figures codes aregrouped in a sector 6 and identical lower case character representativeor Letters codes in the remaining disc area, thereby to simplify therecording of case precedence designator holes by permitting a peripheralportion 7 to be cut away from the upper case or Figures sector 6 of thedisc. Machine function code patterns such as carriage return, space,etc., which have no case will be recorded in both Letters and Figuressector. This arrangement permits, as will hereinafter appear, theproblem of the ambiguity of identical first system code patterns to beresolved.

Similarly disc B has prerecorded therein parallel bit code patterns 8representing corresponding characters of and in accordance with a secondsystem code assignment.

The code patterns 4 and 8 are recorded onthe disc such that codepatterns representing the same character information have the sameangular orientation relative to a reference such as the keyways.

In accordance with the invention the precedence assignment of thecharacterrepresented by each code pattern 8 on the disc B must bemachine recognizable, ac-

cordingly code patterns representing upper and lower case characters aredistinguished by case designators reprecented by the presence andabsence of holes in a precedence or case designator track 9. As withdisc A and as shown in FIGURE 1, rather than recording a hole with eachcode pattern representing an upper case character, all upper casecharacter code patterns are preferably grouped together on the disc B sothat a peripheral arcuate portion 10 coextensive with the areacontaining these code patterns may be cut away thus simplifying therecording of the recognizable precedence or case designator holes. Theuncut peripheral portion designating lower case character code patterns,together with the cut away portion, constituting the precedencedesignator track 9.

Associated with discs A and B are transducer assemblies 11 and 12respectively adapted to sense the perforated code patterns on the discsand also to sense the precedence or case holes in tracks and 9 on discsA and B.

Transducer assemblies suitable for sensing hole patterns may compriselight sources on one side of the discs and light responsive cell-sarrayed on the other side of the discs opposite each track. Thetransducer assemblies will be positioned such that each simultaneouslyreads a code on its corresponding disc representing the same character.

In accordane with the invention code signal patterns of one system thatare to be converted and which are usually -stored in a tape may besupplied to the code converter by a tape reader and corresponding secondsystem codes may be reproduced in a second tape by a record perforator.

A conventional tape reader generally designated by reference numeral 13,which responds to a true signal on tion coextensive with the areacontaining these code a command line 14 may be employed in conjunctionwith the code converter of the invention. Signals will be designatedtrue or false herein, the former being those which initiate a desiredoperation of a circuit element; the latter being the opposite. True andfalse signals may be positive or negative or vice versa. As will beunderstood by those conversant in the art, a true signal on the commandline 14 will cause the reader to cycle whereby during the cycle codesignal patterns will be issued to output lines 15 and the record will beindexed.

The speed of the discs will be determined by the interval that codesignal patterns are issued to output lines 15; the disc speeds beingsuch that they make a complete revolution during the interval that codesignal patterns are on lines 15.

Assuming a 5-8 code conversion is desired, disc A as illustrated willhave 5 bit code patterns 4 representative of all the 5 bit systemcharacters prerecorded therein and disc B the corresponding 8 bit holepatterns 8 prerecorded therein.

The reader output lines 15 are connected to a comparator 16 as are theoutput lines 17 of AND gates 18. One leg of each of the AND gates isconnected to an associated light responsive cell output line 19 of thetransducer assembly 11 and the other legs of the AND gates 18 areconnected to the output of an OR gate 20 adapted to pass, as willhereinafter appear, a true signal only during the interval Figures codesare being sensed or only during intervals that Letters codes are beingsensed. Accordingly, if the reader issues to lines 15 an upper casecharacter representative code as determined by an issued precedingFigures code, when the transducer assembly 11 senses the identical codepattern in the Figures sector 6 of disc A a true signal will begenerated on the output line 21 of the comparator.

To determine which code signal patterns are to be compared i.e. firstsystem Figures or Letters codes, the reader output lines 15 areconnected to a Letters code detector 22 and a Figures code detector 23which recognize these codes and generate a true signal on their outputlines which are connected respectively to the set and reset terminals ofa case memory flip flop 24 whereby the leading edge of a Letters signalwill set the flip flop and the leading edge of a subsequent Figuressignal will reset the flip flop. The two outputs of the flip flop areconnected respectively to a Letters and a Figures AND gate 25 and 26whereby if the flip flop is set the output to the Figures AND gate willbe false and the output to the Letters AND gate will be true; theopposite obtaining when the flip flop is in reset state. The output line19? of the precedence track detecting cell of the transducer assembly isconnected directly to the Figures AND gate 26 and indirectly through aninverter I to the Letters AND gate 25.

If the flip flop 24 is in an assumed Letters or set state, the LettersAND gate output will be true over the interval of time during which noopenings in the precedence track 5 are being detected by the precedencedetector cell of assembly 11. Similarly if the flip flop 24 is in anassumed Figures or reset state, the Figures AND gate output will be trueover the interval of time during which openings in the precedence track5 are being detected. The outputs of the case AND gates 25 and 26 areconnected to the OR circuit 20 whose output, as hereinbefore noted,conditions AND gates 18 to pass bit signal patterns on lines 19 to thecomparator for comparison with code signal patterns on the reader outputlines 15.

In view of the above it will be apparent that if the first code issuedby the reader is a Letters code the flip flop will, if not already in aset state, switch to set state. Accordingly, the Letters gate 25 will beconditioned to pass a Letters precedence signal and the Figures gate 26will be blocked to Figures precedence signals. Letters precedence willbe generated when no openings are detected in the precedence track 5 andFigures precedence signals when openings are detected. Only signalpatterns of codes in the Letters sector of the disc A therefore will bepermitted to pass AND gates 18 for comparison with the code signalpatterns to be converted; gates 18 being blocked to signal patterns ofcodes in the Figures sector 6 as both AND gates 25 and 26 will beblocked over the interval codes in sector 6 are passing the transducerassembly 11.

The output line of the comparator is connected to one leg of each ofeight AND gates 27. The other legs of the AND gates are connected toassociated light responsive cell output lines 28 of the transducerassembly 12 whereby the code signal pattern detected by the transducerassembly 12 is passed through gates 27 during the coincidence intervalto bit flip flops in a buffer storage unit 29 thereby storing the 8 bitcode pattern 8 corresponding to the 5 bit input code pattern. The bitoutput lines 30 of the butter storage unit are connected to an OR gate31 whose output line 32 is connected to one of three inputs to a secondOR gate 33. The output of OR gate 33 is connected to the triggerterminal of a one shot multivibrator 34 which responds to the trailingedge of a true signal passed by OR gate 33. The output signal derivedover the active interval of the multivibrator, which might beincorporated in the reader unit logic, is connected to the readercommand line 14 and its duration need only be sufficient to assure theinitiation of a reader cycle, e.g. an interval at least equivalent tothe pull in time of a cycle clutch magnet. The trailing edge of the truesignal passed by gates 31 and 33 coincides with the resetting of thebuffer unit whereby the reader is cycled only after data in the buffershas been processed as will hereinafter appear.

The butter output lines 30 are also connected to associated legs of ANDgates 35 whose other legs are connected to the output line 36 of asingle shot precedence delay multivibrator 37. The multivibrator 37 isnormally in an inactive or quiescent state such that its output line 36supplies a true signal to all of the gates 35 with the result that theoutput lines 38 of those gates corresponding to the bit signal patternin the butter unit carry signals via OR gates 39 to the input lines 41of a conventional record perforating unit generally designated byreference 42. The record perforating unit is one which will reproducethe code pattern on lines 41 in a tape in response to a start process orcycle initiating clutch signal on a command line 43. The leading edge ofthe command signal may be employed to trigger a one shot delaymultivibrator within the punch logic which will remain in active stateover an interval sufiicient to assure the initiation of a punch cycle,e.g. an interval at least equivalent to the pull in time of a cycleclutch magnet. The command line 43 is connected to the output of an ORgate 44 having all 8 code lines 41 connected as inputs thereto, so thatif any bit is present on lines 41 a process signal will pass the OR gate44.

The output lines 38 of AND gates 35 are also connected to an OR gate 45whose output is connected to a single shot process delay multivibrator46 whose output is connected to the reset line 47 of the buffer 29. Thedelay provided by multivibrator 46 is to assure sufficient time for thepunch unit to record the code signal pattern before the buffers arereset and consequently before the reader emits a subsequent code inresponse to the resetting of the buffer.

In order that second system precedence codes may bereproduced theinvention provides a case condition flip flop 49 and upper and lowercase detectors in the form of AND gates 51 and 52 respectively. Eachcase detector gate has three inputs all of which must be true to gate asignal to the gate output lines 53 and 54. The comparator output line 21is connected to one input of each of the AND gates 51 and 52 and theoutput line 55 of the precedence track detector cell in the transducerassembly 12 is connected to one input of the upper case gate 51 andafter inversion in an inverter 56 to one of the inputs of the lower casegate 52. The third input of the upper case gate 51 is connected to oneof the output lines 57 of the case condition flip flop 49 and the thirdinput of the lower case gate 52 is connected to the other output line 58of the case condition flip flop. The normal state, i.e. lower casestate, of the case condition flip flop 49 is such that output line 57 isnormally true and output line 58 is normally false. The output 53 of theupper case AND gate 51 is connected to the set line 61 of the casecondition flip flop which is adapted to respond to the trailing edge ofthe signal passed by the upper case AND gate 51 and switch to upper casestate. The output of the upper case AND gate 51 is also connected, as isthe output of the lower case AND gate 52, to the input of an OR gate 62whose output is connected to the input line 63 of the single shotmultivibrator 37. Also the upper and lower case AND gate output lines 53and 54 are connected via OR gates 39 to selected input lines 41 of therecord perforator 42 to set up upper and lower case patterns forreproduction in the punch unit. Finally the output line 54 of the lowercase AND gate 52 is also connected to the reset line 64 of the casecondition flip flop 49 which is adapted to respond to the trailing edgeof the signal passed by the lower case AND gate 52 and switch to lowercase state.

The operation of the described converter may be more fully understoodwith reference to FIGURES l and 2. In FIGURE 2 curve 66 represents theoutput of multivibrator 34; curve 67 represents the reader cycle times;curve 68 represents the output of the transducer assemblies; curve 69represents the output of the comparator; curve 71 represents the bufferunit output; curve 72 represents the process delay multivibrator output;curve 73 represents the punch cycle times; curve 74 represents theprecedence delay multivibrator output; and curve 75 represents the casecondition flip flop states.

With the discs rotating, the reader may be initially cycled bymomentarily closing and opening a switch 65 thereby applying a truesignal to gate 33. The trailing edge of the gate output signal willtrigger multivibrator 34 thereby to generate a reader command signal 76at time t (curve 66). After an interval sufficient to enable theenergization of a clutch magnet the reader will begin a sense-feed cycleat time t as illustrated by curve 67. During the sense interval T of thereader cycle the discs will have made one complete revolution wherebyover intervals 1/ T each of the disc codes in the Figures or Letterssectors, as the case may be as determined by the last precedence codeissued by the reader as hereinbefore ex plained, will have been sensedand compared with the code generated by the reader over the reader senseinterval T. Accordingly, a coincidence signal 77 (curve 69) will begenerated sometime e.g. t during the sensing interval T of the readerwhereby AND gates 27 will be conditioned thereby to gate the code signalpattern sensed from disc B to the buffer unit 29 which will be setsimultaneously with the coincidence signal at time t as illustrated bycurve 71.

With the case condition flip flop 49 in an assumed normal lower casestate, if the code issued by the reader and store-d in the buffers is alower case code on disc B, neither of the AND gates 51 or 52 will pass asignal as the input line of the upper case AND gate 51 which isconnected to the precedence track responsive cell of the transducerassembly 12 will not be true, nor will the input line of the lower caseAND gate 52 connected to the output line 58 of the case condition flipflop be true. As neither AND gate 51 or 52 passes a signal, the delaymultivibrator 37 will not be activated; consequently the AND gates 35will be conditioned to and will pass the bit signal pattern in thebuffers to lines 41 at time t also, thereby setting up punch magnets.The perforator unit, in response to the signal from OR gate 44, alsogenerated at will initiate a punch cycle at time 22, whereby the codepattern sensed from disc 11 will be recorded in and a record indexedover the interval t -t As hereinbefore noted the buffers will be resetafter a delay initiated by delay multi vibrator 46 which is triggered attime i by the output from OR gate 45 resulting from passage of bitsignals through AND gates 35; the delay being provided to give therecord perforator suflicient time to reproduce the data and index therecord tape. As shown in FIGURE 2, curve 72, the delay multivibratorremains active until the end of the punch cycle. As hereinbefore notedentry of any bit into storage will generate a signal at the output of ORgate 31 for as long as the buffer unit remains set and when the buffersare reset at time the trailing edge of the signal output of OR gate 31will trigger the multivibrator 34 at time t thereby to initiate anotherreader cycle at a time 1 If the next code resulting in coincidenceillustrated as occurring at time i is an upper case code on disc B allof the inputs to the upper case AND gate 51 will be true and the outputthereof will via OR gate 62 trigger the delay multivibrator 37 at time tto block AND gates 35 thereby to prevent passage of the signal patternin the buffers for an interval sufilcient for an upper case code to bereproduced. This delay interval may also last until the end of the punchcycle time. Reprduction of the precedence code is accomplished byconnecting the upper case AND gate output line 53 selectively to thosebit lines 41 which define the upper case precedence code pattern. Thissets up the punch magnets and initiates via OR gate 44 a punch cycleover the interval t t When delay multivibrator 37 returns to quiescentstate at the end of the punch cycle time, AND gates 35 will then passthe stored bit signal pattern causing multivibrator 46 to be triggeredat time n and the perforating unit to be recycled at time t thereby toreproduce the second system code stored in the buffers. It being notedthat during the punching of a second system precedence code, since ANDgates 35 are blocked, the delay multivibrator 46 will not be activateduntil they open. Accordingly, the butter will remain set over the activeintervals of multivibrators 37 and 46. At the end of the period ofmultivibrator 46, the trailing edge of the signal at the output of ORgate 31 will trigger multivibrator 34 at time 1 etc. Since the casecondition flip flop 49 will have been set by the trailing edge of theupper case AND gate output signal, i.e. time i both gates will beblocked if the next coincident code is another upper case code on disc11 with the result that it will be reproduced immediately.

If however the next coincident code is a lower case code on disc B, allthe inputs to the lower case AND gate 52 will be true and the outputsignal therefrom trigger the delay multivibrator 37 and energizeselected bit lines 41 defining the lower case precedence pattern, whichwill be reproduced after which the disc B code in the buflfers will bereproduced as before, etc.

When a blank code is emitted by the reader, no blank code beingprerecorded on disc A, it is detected by a blank detector 78 alsoconnected to linw 15 whose output line 79 is connected to OR circuit 44.This will cycle the record perforating unit which, since no code patternis on lines 41, will simply index tape. The output of the blank detectoris also connected to an OR gate 81 whose output line 82 is connected viaOR gate 33 whereby the trailing edge of the blank detector true signalwill cause the multivibrator 34 to be triggered. As noted hereinbeforethe output signal of the multivibrator 34 will initiate another readercycle.

If a level upper or lower case precedence code is issued by the reader,no corresponding codes being recorded on disc 10, they are detected inassociated detectors 22 and 23 as hereinbefore noted and whose outputsare also ORed in OR gate 81 thereby to effect a subsequent reader cycle.

While disc records have been disclosed specifically herein with codesrepresented by perforations, it is to be understood that any endlessrecord such as a tape loop may be employed and that codes may berecorded by means other than by perforating.

It should be understood that the foregoing disclosure relates to only apreferred embodiment of the invention and that it is intended to coverall changes and modifications of the example of the invention hereinchosen for the purposes of the disclosure which do not constitutedepartures from the spirit and scope of the invention.

The invention claimed is:

1. Apparatus for converting code patterns of a first system intocorresponding code patterns of a second system wherein code patterns ineach system may be employed twice to represent upper and lower caseinformation, said dual meaning code patterns being distinguishable bylower and upper case precedence code patterns designating that the codepatterns following a precedence code pattern represent lower or uppercase information, and wherein information assigned to upper and lowercase is likely to differ from system to system comprising a first dischaving serially recorded therein on radial lines first system codepatterns,

a second disc having serially recorded therein on radial lines all ofthe corresponding ones of second system code patterns, each of saidradial lines including the case designator of the informationrepresented by the code pattern, the code patterns in said first andsecond discs representing corresponding information being orientated atthe same angular positions with respect to a reference on each of saiddiscs,

a continuously driven shaft,

means mounting said discs with said references in alignment on saidshaft,

first and second transducer means associated respectively with saidfirst and second discs,

said transducer means being positioned to simultaneously readcorresponding code patterns and case designators as the discs aredriven, thereby generating code signal patterns and case designatorsignals,

a source operative to issue first system code signal patterns,

comparator means for generating a gate signal upon coincidence of firstsystem code signal patterns generated by said first transducer means andcode signal patterns issuing from said source,

Second system code signal pattern storage means,

first gate means conditioned by said gate signal to pass the secondsystem code signal pattern generated by said second transducer meansover the interval of coincidence to said storage means,

recording means,

and circuit means operable in response to the simultaneous applicationof said gate signal and to a case designator signal generated during thecoincidence interval by said second transducer means to gate said storedcode signal pattern to said recording means if the case designatorsignal generated is the same as that generated during the previouscoincidence interval, said circuit means being operable to generate acase precedence code signal pattern for recording prior to gating saidstored code signal pattern to said recording means when the casedesignator signal generated by said second transducer means differs fromthat generated during the previous coincidence interval.

2. Apparatus for converting code patterns of a first system intocorresponding code patterns of a second system wherein code patterns ineach system may be employed twice to represent upper and lower caseinformation, said dual meaning code patterns being distinguishable bylower and upper case precedence code patterns designating that the codepatterns following a precedence code pattern represent lower or uppercase information, and wherein information assigned to upper and lowercase is likely to differ from system to system comprising a first dischaving serially recorded therein on radial lines first system codepatterns, each of said radial lines including the case designator of theinformation represented by the code signal pattern,

a second disc having serially recorded therein on radial lines all ofthe corresponding ones of second system code patterns, the code patternsin said first and second discs representing corresponding informationbeing oriented at the same angular positions with respect to a referenceon each of said discs,

a continuously driven shaft,

means mounting said discs with said reference in alignment on saidshaft,

first and second transducer means associated respectively with saidfirst and second discs, said transducer means being positioned tosimultaneously read corresponding code patterns and case designators asthe discs are driven, thereby generating code signal pat terns anddesignator signals,

a source operative to issue first system code signal patterns,

detectors responsive to source issued blank and precedence code signalpatterns to cause said source to issue a subsequent code signal pattern,

a comparator operative to generate an output signal over the interval ofcoincidence of source issued code signal patterns and code signalpatterns generated by said first transducer means,

circuit means conditioned by source issued upper and lower caseprecedence code signal patterns and responsive thereafter to casedesignator signals generated by said first transducer means to gate tosaid comparator only first system code signal patterns whose casedesignator corresponds to the last source issued precedence code signalpattern,

a recorder,

and gate means responsive to said output signal for passing code signalpatterns generated by said second transducer means during thecoincidence interval to said recorder.

3. Apparatus for converting code patterns of a first sys- 7 tem intocorresponding code patterns of a second system wherein code patterns ineach system may be employed twice to represent upper and lower caseinformation, said dual meaning code patterns being distinguishable bylower and upper case precedence code patterns designating that codepatterns following a precedence code pattern represent lower or uppercase information, and wherein information assigned to upper and lowercase is likely to differ from system to system comprising a first dischaving serially recorded therein on radial lines first system codepatterns,

a second disc having serially recorded therein on radial lines all ofthe corresponding ones of second system code patterns, each of saidradial lines including the case designator of the informationrepresented by the code pattern, the code patterns in said first andsecond discs representing the same information being orientated at thesame angular positions with respect to a reference on each of saiddiscs,

a continuously driven shaft,

means mounting said discs with said reference in alignment on saidshaft,

first and second transducer means associated with said first and seconddiscs respectively,

said transducer means being positioned to simultaneously readcorresponding code patterns and associated case designators as the discsare driven, thereby generating code signal patterns and case designatorsignals,

a source operative to issue first system code signal patterns,

a comparator operable to generate an output signal over the interval ofcoincidence of source issued code signal patterns and code signalpatterns generated by said first transducer means,

first circuit means connecting first system code signal patternsgenerated by said first transducer means and said code signal patternsissuing from said source to said comparator,

a recorder,

gate means enabled in response to said comparator output signal to gateto said recorder the second system code signal pattern generated by saidsecond transducer means over the interval of coincidence,

and second circuit means responsive to case designator signals generatedby said second transducer means for passing the gated second system codesignal pattern to said recorder if the case designator signal generatedduring a coincidence interval is the same as the case designator signalgenerated in the previous coincidence interval, and for delaying therecording of said gated second system code signal pattern and generatingprecedence code signal patterns. for recording during the delay periodwhen the case designator signal generated during a coincidence intervaldiifers from that generated in the preceding coincidence interval.

4. Apparatus in accordance with claim 3 wherein said second circuitcomprises a buffer unit for storing code signal patterns passed by saidgate means,

second gate means normally conditioned to pass stored cOde signalpatterns to said recorder,

first delay means responsive to signals passed by said second gate meansfor resetting said buffer unit after an interval suflicient to recordcode signal patterns passed by said second gate means,

third circuit means operative in response to said output signal to passan upper or a lower case designator signal only when the case designatorsignal generated by said second transducer means during a coincidenceinterval differs from that generated in a previous coincidence interval,

second delay means responsive to either a lower or an upper casedesignator signal passed by said third circuit means for blocking saidsecond gate means over an interval necessary to generate and record acase precedence code signal pattern,

and means responsive to said lower and upper case designator signalspassed by said third circuit means for generating a correspondingprecedence code signal pattern.

5. Apparatus in accordance with claim 4 further including meansoperative on said source in response to the resetting of said buffer tocause another first system code signal pattern to issue therefrom.

6. Apparatus as recited in claim 3 wherein said first circuit meansincludes detectors operative in response to source issued lower andupper case precedence and blank code signal patterns to cause saidsource to issue a subsequent code signal pattern.

7. Apparatus as recited in claim 6 wherein each of the radial lines onsaid first disc includes the case designator of the informationrepresented by the code pattern on said radial lines, and wherein saidfirst circuit means is conditionable by source issued upper and lowercase precedence code signal patterns and responsive thereafter to casedesignator signals generated by said first transducer means to gate tosaid comparator only first system code signal patterns whose casedesignator corresponds to the last source issued precedence code signalpattern.

8. Apparatus in accordance with claim 7 wherein said third circuit meanscomprises upper and lower case gates operable when conditioned to passupper and lower case designator signals,

and a bistable circuit operable from lower to upper case state and fromupper to lower case state in response to upper and lower case designatorsignals passed by said upper and lower case gates respectively, saidupper case gate being conditioned when said bistable circuit is in lowercase state and being operable during a coincidence interval in responseto an upper case designator signal, said lower case gate beingconditioned when said bistable circuit is in upper case state and beingoperable during a coincidence interval in response to a lower casedesignator signal.

References Cited by the Examiner UNITED STATES PATENTS 8/1965 Von Kummer340347

1. APPARATUS FOR CONVERTING CODE PATTERNS OF A FIRST SYSTEM INTOCORRESPONDING CODE PATTERNS OF A SECOND SYSTEM WHEREIN CODE PATTERNS INEACH SYSTEM MAY BE EMPLOYED TWICE TO REPRESENT UPPER AND LOWER CASEINFORMATION, SAID DUAL MEANING CODE PATTERNS BEING DISTINGUISHABLE BYLOWER AND UPPER CASE PRECEDENCE CODE PATTERNS DESIGNATING THAT THE CODEPATTERNS FOLLOWING A PRECEDENCE CODE PATTERN REPRESENT LOWER OR UPPERCASE INFORMATION, AND WHEREIN INFORMATION ASSIGNED TO UPPER AND LOWERCASE IS LIKELY TO DIFFER FROM SYSTEM TO SYSTEM COMPRISING A FIRST DISCHAVING SERIALLY RECORDED THEREIN ON RADIAL LINES FIRST SYSTEM CODEPATTERNS, A SECOND DISC HAVING SERIALLY RECORDED THEREIN ON RADIAL LINESALL OF THE CORRESPONDING ONES OF SECOND SYSTEM CODE PATTERNS, EACH OFSAID RADIAL LINES INCLUDING THE CASE DESIGNATOR OF THE INFORMATIONREPRESENTED BY THE CODE PATTERN, THE CODE PATTERNS IN SAID FIRST ANDSECOND DISCS REPRESENTING CORRESPONDING INFORMATION BEING ORIENTATED ATTHE SAME ANGULAR POSITIONS WITH RESPECT TO A REFERENCE ON EACH OF SAIDDISCS, A CONTINUOUSLY DRIVEN SHAFT, MEANS MOUNTING SAID DISCS WITH SAIDREFERENCES IN ALIGNMENT ON SAID SHAFT, FIRST AND SECOND TRANSDUCER MEANSASSOCIATED RESPECTIVELY WITH SAID FIRST AND SECOND DISCS, SAIDTRANSDUCER MEANS BEING POSITIONED TO SIMULTANEOUSLY READ CORRESPONDINGCODE PATTERNS AND CASE DESIGNATORS AS THE DISCS ARE DRIVEN, THEREBYGENERATING CODE SIGNAL PATTERNS AND CASE DESIGNATOR SIGNALS, A SOURCEOPERATIVE TO ISSUE FIRST SYSTEM CODE SIGNAL PATTERNS, COMPARATOR MEANSFOR GENERATING A GATE SIGNAL UPON COINCIDENCE OF FIRST SYSTEM CODESIGNAL PATTERNS GENERATED BY SAID FIRST TRANSDUCER MEANS AND CODE SIGNALPATTERNS ISSUING FROM SAID SOURCE,